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March 2004
(R)
AS7C31024B
3.3V 128K X 8 CMOS SRAM Features
* Industrial and commercial temperatures * Organization: 131,072 words x 8 bits * High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
* Easy memory expansion with CE1, CE2, OE inputs * TTL/LVTTL-compatible, three-state I/O * 32-pin JEDEC standard packages
300 mil SOJ 400 mil SOJ 8 x 20mm TSOP 1 8 x 13.4mm sTSOP 1
* Low power consumption: STANDBY
- 18 mW / max CMOS
* ESD protection 2000 volts * Latch-up current 200 mA
* 6T 0.18u CMOS technology
Pin arrangement Logic block diagram
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
32-pin SOJ (300 mil) 32-pin SOJ (400 mil)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7
Row decoder
512 x 256 x 8 Array (1,048,576)
Sense amp
32-pin (8 x 20mm) TSOP I 32-pin (8 x 13.4mm) sTSOP1
I/O0 WE OE CE1 CE2
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
Selection guide
-10
-12 12 6 65 5
-15 15 7 60 5
AS7C31024B
Column decoder
Control circuit
A9 A10 A11 A12 A13 A14 A15 A16
AS7C31024B
-20 20 8 55 5
Unit ns ns mA mA
Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current
10 5 70 5
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Alliance Semiconductor
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Copyright (c) 2003 Alliance Semiconductor. All rights reserved.
AS7C31024B
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Functional description
The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 - -65 -55 - Max +5.0 VCC +0.50 1.0 +150 +125 20 Unit V V W C C mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
Key: X = don't care, L = low, H = high
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Recommended operating conditions
Parameter Supply voltage Input voltage Ambient operating temperature
VIL = -1.0V for pulse width less than 5ns
VIH = VCC + 1.5V for pulse width less than 5ns
Symbol VCC VIH VIL commercial TA
Min 3.0 2.0 -0.5 0
Nominal 3.3 - - -
Max 3.6 VCC + 0.5 0.8 70
Unit V V V C
DC operating characteristics (over the operating range)1
-10 Parameter Input leakage current Output leakage current Operating power supply current Sym |ILI| |ILO| Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC VCC = Max, CE1 VIL, CE2 VIH, f = fMax, IOUT = 0 mA VCC = Max, CE1 VIH and/or CE2 VIL, f = fMax VCC = Max, CE1 VCC-0.2V and/ or CE2 0.2V VIN 0.2V or VIN VCC -0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min
Min Max Min
-12
Max Min
-15
Max Min
-20
Max
Unit A A
- -
1 1
- -
1 1
- -
1 1
- -
1 1
ICC
-
70
-
65
-
60
-
55
mA
ISB Standby power supply current ISB1
-
30
-
25
-
20
-
20 mA
-
5
-
5
-
5
-
5
Output voltage
VOL VOH
- 2.4
0.4 -
- 2.4
0.4 -
- 2.4
0.4 -
- 2.4
0.4 -
V V
Capacitance (f = 1 MHz, Ta = 25 C, VCC = NOMINAL)2
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE1, CE2, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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Read cycle (over the operating range)3,9,12
-10 Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change CE1 low to output in low Z CE2 high to output in low Z CE1 high to output in high Z CE2 low to output in high Z OE low to output in low Z OE high to output in high Z Power up time Power down time Symbol Min tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD 10 - - - - 3 3 3 - - 0 - 0 - Max - 10 10 10 5 - - - 3 3 - 5 - 10 12 - - - - 3 3 3 - - 0 - 0 - -12 Min Max - 12 12 12 6 - - - 3 3 - 6 - 12 15 - - - - 3 3 3 - - 0 - 0 - -15 Min Max - 15 15 15 7 - - - 4 4 - 7 - 15 20 - - - - 3 3 3
- -
-20 Min Max Unit ns 20 20 20 8
- - -
Notes 3 3, 12 3, 12 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12
ns ns ns ns ns ns ns ns ns ns ns ns ns
5 5 - 8 - 20
0 - 0 -
Key to switching waveforms
Rising input Falling input Undefined / don't care
Read waveform 1 (address controlled)3,6,7,9,12
tRC Address DOUT tAA Data valid tOH
Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12
CE1 CE2 OE DOUT tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% ICC ISB tOE tOLZ tOHZ tCHZ1, tCHZ2 tRC1
Supply current
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Write cycle (over the operating range)11, 12
-10 Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW1 tCW2 tAW tAS tWP tWR tAH tDW tDH tWZ tOW Min 10 8 8 8 0 7 0 0 5 0 - 1 Max - - - - - - - - - - 5 - 12 9 9 9 0 8 0 0 6 0 - 1 -12 Min Max - - - - - - - - - - 6 - 15 10 10 10 0 9 0 0 8 0 - 1 -15 Min Max - - - - - - - - - - 7 - 20 12 12 12 0 12 0 0 10 0 - 1 -20 Min Max Unit Notes - - - - - - - - - - 8 - ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 12
Write waveform 1 (WE controlled)10,11,12
tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tWR tAH
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Write waveform 2 (CE1 and CE2 controlled)10,11,12
tAW Address tAS CE1 CE2 tWP WE tWZ DIN DOUT tDW Data valid tDH tCW1, tCW2 tWC tAH tWR
AC test conditions
- - - - Output load: see Figure B. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V.
Thevenin equivalent: 168 DOUT +1.728V +3.3V 320 +3.0V GND 90% 10% 2 ns 90% 10% DOUT 255 C13
Figure A: Input pulse
GND Figure B: 3.3V Output load
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, and B. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE1 and OE are low and CE2 is high for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. N/A
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Package dimensions
D e E1E2
32-pin SOJ 300 mil Min A A1
B c A1 b Seating Plane A
32-pin SOJ 400 mil Min 0.132 0.025 0.105 0.026 0.015 0.007 0.820 0.354 0.395 0.435 Max 0.146 0.115 0.032 0.020 0.013 0.830 0.378 0.405 0.445
Max 0.145 0.105 0.032 0.020 0.010 0.830 0.275 0.305 0.340
0.128 0.025 0.095 0.026 0.016 0.007 0.820 0.255 0.295 0.330
Pin 1
A2 B b c D E E1 E2 e
A2 E
0.050 BSC
0.050 BSC
b
e c D Hd L A2 A A1
32-pin TSOP 8x20 mm Min A A1 A2 b c D
pin 1 pin 32
Max 1.20 0.15 1.05 0.27 0.21 18.50 8.10 20.20 0.70 5
- 0.05 0.95 0.17 0.10 18.30 7.90 19.80 0.50 0
e E Hd L
0.50 nominal
E
pin 16
pin 17
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Alliance Semiconductor
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AS7C31024B
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Ordering codes
Package \ Access time Plastic SOJ, 300 mil Plastic SOJ, 400 mil TSOP1 8x20 mm sTSOP1 8 x 13.4mm
Temp Commercial
10 ns AS7C31024B-10JC
12 ns AS7C31024B-12TJC AS7C31024B-12JC AS7C31024B-12TC
15 ns AS7C31024B-15TJC AS7C31024B-15JC AS7C31024B-15TC
20 ns AS7C31024B-20TJC AS7C31024B-20JC AS7C31024B-20TC
Commercial AS7C31024B-10TJC Commercial AS7C31024B-10TC
Commercial AS7C31024B-10STC AS7C31024B-12STC AS7C31024B-15STC AS7C31024B-20STC
Note: Add suffix `N' to the above part number for lead free parts (Ex. AS7C31024B-10TJCN)
Part numbering system
AS7C X 1024B -XX X Package: T = TSOP1 8x20 mm ST = sTSOP1 8 x 13.4 mm J = SOJ 400 mil TJ = SOJ 300 mil X Temperature range C = Commercial, 0 C to 70 C X
SRAM Device Access 3 = 3.3 V CMOS prefix number time
N=Lead Free Part
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Alliance Semiconductor
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AS7C31024B
(R)
(R)
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: AS7C31024B Document Version: v.1.2
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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